This circuit works in conjunction with Richard Stibbon's Mark 3 BT Roll Scanner Interface.
The circuit uses an XOR gate with delay in one path to generate a pulse on the rising and falling edge of the CIS clock signal from the parallel port. The pulses are shaped with a one shot multivibrator. Two bits of CIS data from the comparator are clocked into a shift register, which is read by the parallel port. The design will support a second CIS for two-color hole and word scanning. The breadboard prototype operates with an input frequency of 500 KHZ, giving a CIS clock rate of 1 MHZ.
The optimum values for the resistors and capacitors controlling the pulse width of the one shot multivibrator have not been determined. The breadboard prototype used 10k ohms and no capacitor. The repeatability of the XOR circuit with only gate propagation delay has not been determined. An RC network or solid-state delay line between the first and second gate may be needed.
I have only tested the module by itself, using a signal generator and scope. It should be tested with the Mark 3 board before it is implemented on a PC board.
The documentation package MK 3 clock doubler rev A.zip contains PDF files of the circuit diagram and IC datasheets. The Visio schematic design file is also included.
Wes
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